This invention grew out of a need to improve the methods of semiconductor device miniaturization and to thereby enhance production of very efficient integrated circuitry. The methods of this invention are particularly adapted to the problems confronted in ultra large scale integration (ULSI) and the production of transistors in the sub-half-micron regime. However, practitioners skilled in the art will also appreciate that the methods of this invention can be applied to very large scale integration (VLSI) and the production of transistors in the micron regime.
Among the problems that become particularly pronounced as transistor size decreases are source-drain punchthrough and hot electron susceptibility. These problems are commonly solved by forming graded junction regions to decrease the abruptness of the transition from a conductively doped source or drain region to the bulk substrate surrounding the region.
There are numerous types of graded junction regions. Two commonly used graded junction regions are the regular Lightly Doped Drain (LDD) region and the halo region.
The regular LDD regions are often utilized to reduce the electric field under a gate and to thereby reduce the energy of hot electrons within a Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) device. This reduction in energy can reduce the damage caused to the MOSFET device by such hot electrons. The regular LDD regions comprise a conductivity enhancing dopant of the same conductivity type as the adjacent source or drain regions. Thus, in an NMOS device the regular LDD regions comprise an n-type conductivity enhancing dopant, and in a PMOS device the regular LDD regions comprise a p-type conductivity enhancing dopant.
Halo regions are commonly used to improve the punchthrough resistance of a transistor. Halo regions comprise conductivity enhancing dopant of a different conductivity type than the source or drain regions adjacent the halo region. Thus, in an NMOS device the halo regions comprise a p-type conductivity enhancing dopant, and in a PMOS device the halo regions comprise an n-type conductivity enhancing dopant.
A significant problem encountered in the formation of graded junction regions arises from the additional masking steps used in forming these regions. Each additional masking step carries with it a risk of error due to mask misalignment. Accordingly, the probability of creating a fully functional, high-quality integrated circuit decreases as a function of the number of additional masking steps required to form the circuit. It is an object of this invention to reduce the number of masking steps used for graded junction formation during transistor fabrication generally, and during CMOS fabrication specifically.
In one aspect, this invention teaches a method of simultaneously forming regular LDD and halo regions for paired NMOS and PMOS devices of CMOS circuitry. In another aspect, this invention teaches a method for enhancing the dopant concentration of regular LDD regions and/or halo regions after the formation of a gate and the provision of spacers and/or source/drain regions adjacent to the gate.